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| MIC50398/50399 Micrel MIC50398/MIC50399 Six Decade Counter / Display Decoder Not Recommended for New Designs General Description The MIC50398/9 is an ion-implanted, P-channel MOS six-decade synchronous up/down-counter/display driver with storage latches. The counter can be loaded digit-by-digit with BCD data. The counter has an asynchronous-clear function. Scanning is controlled by the scan oscillator input which is self-oscillating or can be driven by an external signal. The contents of the counter can be transferred into the 6-digit latch which is then multiplexed from MSD to LSD in BCD or 7-segment format to the output. These devices are intended to interface directly with the standard CMOS logic families. Features * * * * * * * * Single power supply Schmitt-Trigger on the count-input Six decades of synchronous up/down counting Look-ahead carry or borrow Loadable counter Multiplexed seven-segment outputs MIC50398N Multiplexed BCD outputs, MIC50399N Internal scan oscillator Pin Connection V SS SET a b c SEGMENTS d e f g 1 2 3 4 5 6 7 8 9 MIC50398CN 28 27 26 25 24 UP/DOWN CARRY COUNT INHIBIT COUNT INPUT LOAD COUNTER BCD OUTPUT DIGIT STROBES V SS SET NC NC A B C D STORE 1 2 3 4 5 6 7 8 9 MIC50399CN 28 27 26 25 24 23 UP/DOWN ZERO CARRY COUNT INHIBIT COUNT INPUT LOAD COUNTER 23 D 6 22 D 5 21 D 4 20 D 3 19 D 2 18 D 1 17 16 15 V DD SCAN CLEAR 22 D 6 21 D 5 20 D 4 19 D 3 18 D 2 17 D 1 16 15 V DD SCAN DIGIT STROBES STORE 10 C D 11 COUNTER BCD INPUTS C C 12 C B 13 C A 14 C D 10 COUNTER BCD INPUTS C C 11 C B 12 C A 13 CLEAR 14 Ordering Information Part Number MIC50398CN MIC50399CN Temp. Range 0C to 70C 0C to 70C Package 28-pin Plastic DIP 28-pin Plastic DIP Segment Identification a f e d 8-10 August 1998 g b c MIC50398/50399 Micrel The carry output goes high with the leading edge of the count input at the count of 000000 when counting up or at 999999 when counting down and goes low with the negative going edge of the same count input. During a load counter operation the carry output is inhibited. A count frequency of 1.5 MHz can be achieved if the zero output and carry output are not used. These outputs do not respond at this frequency due to their output delay illustrated on the timing diagram. Operations: Six Decade Counter, Latch The six decade counter is synchronously incremented or decremented on the positive edge of the count input signal. A Schmitt trigger on this input provides hysteresis for protection against both a noisy environment and double triggering due to a slow rising edge at the count input. The count inhibit can be changed in coincidence with the positive transition of the count input. Count inhibit must remain high while the count input is high to inhibit counting. The counter will increment when up/down input is high (VSS) and will decrement when up/down input is low. The up/down input can be changed 0.75 s prior to the positive transition of the count input. The clear input is asynchronous and will reset all decades to zero when brought high but does not affect the six digit latch or the scan counter. As long as store input is low, data is continuously transferred from the counter to the display. Data in the counter will be latched and displayed when store input is high. Store can be changed in coincidence with the positive transition of the count input. The counter is loaded digit by digit corresponding to the digit strobe outputs. BCD thumb wheel switches with four diodes per decade connected between the digit strobe outputs and the BCD inputs is one method to supply BCD data for loading the counter decades. The load counter pulse must be at VSS 2 s prior to the positive transition of the digit strobe of the digit to be loaded. The load counter pulse may be removed after the positive transition of the digit strobe since the chip internally latches this signal. The BCD data to be loaded must be valid through the negative transition of the digit strobe. BCD & Seven Segment Outputs BCD or seven segment outputs are available. Digit strobes are decoded internally by a divide by six Johnson counter. This counter scans from MSD to LSD. By bringing the SET input low, this counter will be forced to the MSD decade count. During this time the segment outputs are blanked to protect against display burn out. BCD outputs are valid for MSD when SET is low. Applying VSS to SET allows normal scan to resume. Digit 6 output is active (VSS) until the next scan clock pulse brings up digit 5 output. The segment outputs and digit strobes are blanked during the interdigit blanking time. Typically the interdigit blanking time is 3 to 10 microseconds when using the internal scan oscillator. BCD output data changes at the beginning of the interdigit blanking time. Therefore the BCD output data is valid when the positive transition of a digit output occurs. BCD outputs are on MIC50399 only. Scan Oscillator The counters have an internal scan oscillator. The frequency of the scan oscillator is determined by an external capacitor between VSS or VDD and scan input. The wave form present on the scan oscillator input is triangular in the self oscillate mode. An external oscillator may also be used to drive the scan input. In the external drive mode the interdigit blanking time will be the sum of the negative dwell period of the external oscillator and the normal self oscillate blanking time. (310 s). Display brightness can be controlled by the duty cycle of the external scan oscillator. Typically, the scan oscillator will oscillate at the following frequencies with these nominal capacitor values from VSS to scan input. CIN 820 pF 470 pF 120 pF Min 1.4 kHz 2.0 kHz 7.0 kHz Max 4.8 kHz 6.8 kHz 20 kHz 8 Inputs, Outputs The seven segment outputs are open drain capable of sourcing 10mA average current per segment over one digit cycle. Segments are on when at VSS. The Carry, Zero, BCD and digit strobe outputs are push pull and are on when at VSS. All inputs except Counter BCD and SCAN inputs are high impedance CMOS compatible. Two basic outputs originate from the counter: zero output, and carry output. Each output goes high on the positive (VSS) going edge of the count input under the following conditions: Zero output goes high for one count period when all decades contain zero. During a load counter operation the zero output is inhibited. Zero output is on the MIC50399 only. August 1998 8-11 MIC50398/50399 Micrel LED DIS Functional Diagram *50399 Only **50398 Only ** BCD OUT * 4 7 7 SEGMENT DECODER 6 6:1 MUX STORE 6 DIGIT LATCH 6 SCAN COU COUNT INHIBIT COUNT UP/DOWN CLEAR 6 DIGIT BCD UP/DOWN COUNTER 8-12 August 1998 MIC50398/50399 Micrel Absolute Maximum Ratings* Voltage on Any Terminal Relative to VSS +0.3V to -20V Operating Temperature Range (Ambient) 0C to +70C Storage Temperature Range (Ambient) -40C to +100C *Operating device. above absolute maximum ratings may damage the Maximum Operating Conditions Symbol TA VSS ISS BV PD Parameter Operating Temperature Supply voltage (VDD = 0V) Supply Current Break Down Voltage (Segment only @ 10 A) Power Dissipation Min 0 10 Max 70 15 40 VSS - 26 670 Units C V mA V mW 1 MIC50398 only 2 Notes Electrical Characteristics (VDD = 0V, VSS = +10.0V to +15.0, 0C TA 70C) Static Operating Conditions Symbol VIL VIH VOL VOH IOH Parameter Input Low Voltage, "0" Input High Voltage, "1" Output Voltage "0" @ 30 A Output Voltage "1" @ 1.5 mA Output Current "1" Digit strobes Segment outputs Scan Input Pullup Current @ 0 V Scan Input Pulldown Current @ 15 V SET Input Pullup Current @ 0V 2 5 0.8 VSS 3.0 10.0 5.5 40 60 Min VDD VSS - 1 Max 0.2 VSS VSS 0.2 VSS Units V V V V mA mA mA A A 3 4 4 5 6 Notes 8 ISCAN ISCAN ISET Note 1: ISS with inputs and outputs open at 0C. 33 mA at 25C and 28 mA at 70C. This does not include segment current. Total power per segment must be limited not to exceed power dissipation of package. (JA = 100C/Watt) Note 2: All outputs loaded. Note 3: MIN VIH from CA CB CC CD inputs is VSS - 3.5 V. Those inputs have internal pulldown resistors to VDD. Note 4: This applied to the push pull CMOS compatible outputs. Does not include digit strobes on segment outputs. Note 5: For VOUT = VSS - 2.0 Volts. Average value over one digit cycle. Note 6: For VOUT = VSS - 3.0 Volts. Average value over one digit cycle. August 1998 8-13 MIC50398/50399 Micrel Timing COUNT t UDS UP/DOWN t UDS t CIS t CIS COUNT INHIBIT t SS STORE t PCW CLEAR t SPW t CS COUNT t OA ZERO t OH t CH t CA CARRY SCAN tL LOAD COUNTER Loading Counter, Register (1 Digit) t LS LOAD COUNTER t DV BCD DATA INPUT tLS 2.0 s min NOTE: REF. TO POSITIVE TRANSITION OF DIGIT OUTPUT tDV 2.0 S min NOTE: REF. TO NEGATIVE EDGE OF DIGIT OUTPUT DIGIT OUTPUT 6 DIGIT OUTPUT 5 ETC COUNT INPUT, CARRY ZERO OUTPUT INHIBITED DURING THIS TIME COUNT INPUT t OA ZERO OUTPUT t OH t CA t CH CARRY OUTPUT NOTE: The inhibit function of the zero or carry outputs does not end when the Load Counter input goes to a "0" unless that transition occurs during interdigit blanking period at least 2.0 s prior to a positive transition of a digit output. 8-14 August 1998 MIC50398/50399 Micrel Dynamic Operating Conditions Symbol fCI fSI tCPW tSPW tSS tCIS tUDS tCPW tCS tOA tOH tCA tCH tL Parameter Count Input Frequency Scan Input Frequency Count Pulse Width Store Pulse Width Store Setup Time Count Inhibit Setup Time Up/Down setup Time Clear Pulse Width Clear Setup Time Zero Access Time Zero Hold Time Carry Access Time Carry Hold Time Load Time 1/6 fSI Min 0 0 325 2.0 0 0 -0.75 2.0 -0.5 3.0 1.5 1.5 0.9 Max 1.5 20 Units MHz kHz ns s s s s s s s s s s 10 10 10 10 10 10 MIC50399 only 10 MIC50399 only 10 11 12 9 Notes 7,8 Note 7: Measured at 50% duty cycle. Note 8: If carry or zero outputs are used, the count frequency will be limited by their respective output times. Note 9: The count pulse width must be greater than the carry access time when using the carry output. Note 10: The positive edge of the count input is the t = 0 reference. Note 11: Measured from negative edge of count input. Note 12: Time to load one digit. 8 August 1998 8-15 |
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